Integrated circuit devices, commonly known as chips, continue to become more powerful and complex as semiconductor manufacturing technologies have advanced. Whereas early integrated circuit devices included fewer than one hundred transistors, it is now common to integrate several million transistors into a single integrated circuit device. This increased transistor count enables some operations that once required several integrated circuit devices to now be implemented in a single integrated circuit device, often providing greater performance at a lower cost.
One effect of the increase in the complexity of integrated circuit devices, however, is that testing of the manufactured devices has become significantly more complex and time consuming. Early integrated circuit devices often had enough input/output pins to enable all of the relevant internal operations of a device to be monitored to ensure that the device operated in its intended manner. However, with current designs incorporating millions of transistors and numerous high level functions, it is impracticable to provide sufficient input/output connectivity to enable direct monitoring of device operation.
To address these limitations, many integrated circuit devices now incorporate a boundary scan architecture within the logic circuitry of a device to provide access to many of the internal circuits of the device. With a boundary scan architecture, one or more serial scan chains, or scan paths, of latches are coupled to dedicated pins of a device, with individual latches embedded within the logic circuitry of the device at key points of the design. The latches, when not specifically configured to operate as a scan chain, do not otherwise alter the functionality of the device. However, when the latches are configured in a specific mode, the latches together operate as a shift register so that data may be shifted into the chain of latches from a single source to simulate different conditions, and so that data generated within a device may be shifted out through a single output. Thus, with a boundary scan architecture, the current state of various circuits in a device at any given time may be recorded and later accessed via external equipment to verify the operation of a manufactured device.
Additional efforts to enhance device testability incorporate built-in self-test (BIST) circuitry into individual devices to perform predetermined testing operations on the device without the assistance of external circuitry, e.g., upon power-up of a device. For example, for logic devices such as processors and controllers, logical built-in self-test (LBIST) circuitry may be used to apply pseudo-random test patterns to logic gates to verify their correct operation.
Similarly, array built-in self-test (ABIST) circuitry may be used to apply test patterns to memory arrays embedded in an integrated circuit device to verify the correct operation of such arrays. ABIST typically applies address, data and control information to an array and clocks the array to first write test patterns to the array. Thereafter, ABIST again applies address, data and control information and clocks the array to read out the stored test patterns to a scan chain or a Multiple-Input Shift Register (MISR). Differences between the written test patterns and the output data indicate potential defects in an array.
One common failure mechanism that arises relatively early in the design of an integrated circuit device is a broken scan chain, typically resulting from the manufacture of a defective latch in the scan chain. Conventional attempts to detect broken scan chains include flush and scan tests. A flush test, for example, holds the clock signals to each latch in a scan chain in an active state such that a value asserted on the input to the scan chain propagates through all of the latches to the scan chain output. By applying logic one and logic zero values to the scan chain input, an identical value should propagate to the scan chain output (taking into account any inversions in the scan chain). Otherwise, a broken scan chain is likely present.
A scan test, on the other hand, consists of applying a string of alternating logic values (e.g., 00 11 00 11 . . . ) to the input of a scan chain, and stepping the data along the scan chain by pulsing the clock inputs thereto. A break in a scan chain (typically as a result of a fault that causes a clock line to remain asserted), is typically indicated if anything other than the original input string is detected at the output of the scan chain.
While flush and scan tests are capable of detecting broken scan chains, they are not capable of detecting where the break in a scan chain is located. Moreover, since many of the other tests employed in chip testing utilize the scan chains to pass data to, or retrieve data from, an integrated circuit device, these tests cannot themselves be utilized to assist in diagnosing broken scan chains.
Therefore, a significant need exists in the art for an improved manner of detecting a defect in a scan chain, and in particular, for a manner of identifying a specific location of a defect in a scan chain.